The present invention relates to a method for fabricating a BiCMOS device: and a structure thereof, and more particularly relates to a BiCMOS device, in which a base layer is formed for a bipolar transistor by a selective epitaxial growth technique.
A bipolar transistor has been used as a circuit element with high-speed and high-current characteristics. Particularly, a type of high-performance bipolar transistor is called a xe2x80x9cself-aligned base transistorxe2x80x9d, an example of which is disclosed in U.S. Pat. No. 4,319,932. According to a technique disclosed in this patent, by implanting a dopant through an implantation window, raised sub-collector, intrinsic base and emitter layers are formed.
Also, a technique of forming a heterojunction for enhancing the performance of a bipolar transistor is known. To form a heterojunction in a transistor with a silicon substrate for that purpose, a technique of using a material with a bandgap wider than that of Si for a base layer (e.g., GaP, SiC or amorphous Si grown on a base layer) and a technique of using a material with a narrow bandgap (e.g., SiGe compound semiconductor for a base; see Japanese Laid-Open Publication No. 6-77245) have been developed. Particularly, as a method for fabricating a bipolar transistor including a precisely controlled base layer by selective epitaxial growth, a method disclosed in Japanese Laid-Open Publication No. 8-83805, for example, is known. In this method, a silicon dioxide film with a thickness of about 140 nm as an insulator, and a polysilicon film for base extended electrode are stacked and then part of the polysilicon film, in which an emitter will be formed, is removed to form an opening. Then, part of the silicon dioxide film exposed on the bottom of the opening is isotropically etched to expose part of a silicon substrate and then a silicon film to be connected to crystalline silicon for a base and the polysilicon film for a base extended electrode is deposited on the part of the silicon substrate exposed inside the opening. A main object of this method is to reduce a junction leakage around a base layer and is also characterized in that the structure of a transistor can be downsized and parasitic capacitance and parasitic resistance can be reduced by utilizing the selective epitaxial growth technique.
Also, a so-called xe2x80x9cBiCMOS devicexe2x80x9d, including a bipolar transistor and CMOS transistors formed on the same semiconductor substrate, is well-known.
However, where a base layer for a bipolar transistor is formed by the known selective epitaxial growth, the following problems arise.
Firstly, if an insulating film with a thickness (about 140 nm) greater than that of the base layer subjected to the selective epitaxial growth is used, problems often arise in terms of the yield and productivity. For example, the type of SiGe epitaxial growth (selective or non-selective growth) and the thickness of a P+-type single crystal silicon layer to be electrically connected to the polysilicon for base extended electrode are difficult to control.
Also, a fabrication process for a BiCMOS device is performed with the characteristics of its CMOS block respected. However, if the fabricating method for a bipolar transistor utilizing the known selective epitaxial growth is applied to the fabrication process for a BiCMOS device as it is, the number of process steps and the fabrication cost increase significantly.
Furthermore, as the thickness of a base layer is further reduced in the future, adverse effects of undue stress should be brought about in an interface between dissimilar materials, e.g., an interface between the base layer, which is an epitaxially grown layer, and an insulating layer, due to a difference in thermal expansion coefficients.
In view of these problems, the present invention provides a method for fabricating a BiCMOS device including a heterojunction bipolar transistor that can be controlled under a fewer restrictions by utilizing a selective epitaxial growth technique. The present invention also provides a method for fabricating a BiCMOS device that can lessen the adverse effects of undue stress, which should be applied to the interface between dissimilar materials in the near future.
A semiconductor device according to the present invention includes: a substrate having a semiconductor layer at least in a surface region thereof; a collector layer of a first conductivity type, which is provided in the semiconductor layer; a base extended electrode, which is provided over the collector layer and is formed out of a conductor film with a first opening; a base undercoat insulating film, which is interposed between the substrate and the base extended electrode and has a second opening wider than the first opening; a base layer of a second conductivity type, which is provided on the semiconductor layer and includes a peripheral portion and a center portion, the peripheral portion being in contact with a lower edge of the base extended electrode around a periphery of the first opening, the center portion being located in an inner region of the first opening of the base extended electrode and deposited thicker than the peripheral portion; an emitter layer of the first conductivity type, which is provided inside the first opening of the base extended electrode and is in contact with the upper surface of the center portion of the base layer; and an insulator film interposed between a side face of the first opening of the base extended electrode and the base and emitter layers.
In this structure, the peripheral portion of the base layer is thinner than the center portion of the base layer, and a stress, resulting form a difference in thermal expansion coefficient between the base layer and base undercoat insulating film, can be reduced. Specifically, where the edge of a base layer is in direct contact with a base extended electrode in a known bipolar transistor, a base undercoat insulating film is thicker than the base layer, which needs to have a thickness between 50 nm and 100 nm ordinarily. Therefore, a great stress, resulting from a difference in thermal expansion coefficient between them, is applied to the base layer and so on. As a result, where a heterojunction is formed between the base and collector layers, the characteristic of the bipolar transistor might be degraded due to a relaxed strain. In contrast, in the present invention, by reducing the thickness of the base undercoat insulating film, the stress, resulting form the difference in thermal expansion coefficient between the base undercoat insulating film and base layer, can be reduced, thus suppressing the degradation in characteristic of the bipolar transistor.
The lower edge of the base extended electrode around the periphery of the first opening may be extended to be in contact with the collector layer along a side face of the second opening of the base undercoat insulating film. And the peripheral portion of the base layer may be separated from the base undercoat insulating film by the lower edge of the base extended electrode. As a result, the creation of the stress, resulting from the difference in thermal expansion coefficient, can be further suppressed.
The semiconductor layer may be made of Si single crystals. The base layer may be made of SiGe single crystals. The emitter layer may be made of Si single crystals. And the semiconductor device may be a heterojunction bipolar transistor.
Alternatively, the collector layer may be made of Si single crystals. The base layer may be made of SiGeC single crystals. And the emitter layer may be made of Si single crystals.
And the semiconductor device may be a heterojunction bipolar transistor. In such a case, by changing the composition of the SiGeC single crystals, the strain and the function of the bipolar transistor can be controlled appropriately and easily.
An MIS transistor, including a gate insulating film provided on the substrate and a gate electrode provided on the gate insulating film, may be formed on the substrate. And the base extended electrode of the bipolar transistor and the gate electrode of the MIS transistor may be formed out of the same conductor film. Then, the number of process steps can be cut down and the fabrication cost can be reduced.
An inventive semiconductor device fabricating method is used for fabricating a semiconductor device including a bipolar transistor that comprises: a collector layer of a first conductivity type, formed out of a first semiconductor layer; a base layer of a second conductivity type, formed out of a second semiconductor layer; an emitter layer of the first conductivity type, formed out of a third semiconductor layer; a base extended electrode formed out of a first conductor film; and an emitter extended electrode formed out of a second conductor film. The method includes the steps of: (a) forming a first insulator film on the first semiconductor layer existing at least in a surface region of a substrate; (b) forming the first conductor film on the first insulator film; (c) forming a first opening in the first conductor film to expose the first insulator film; (d) etching isotropically part of the first insulator film, which part is exposed inside the first opening, to form a second opening, which is wider than the first opening, in the first insulator film, thereby exposing the first semiconductor layer; (e) forming the second semiconductor layer, including a peripheral portion and a center portion, on the first semiconductor layer by an epitaxial growth process, the peripheral portion being in contact with a lower edge of the first conductor film around a periphery of the first opening, the center portion being located in an inner region of the first opening of the first conductor film and deposited thicker than the peripheral portion; (f) forming the third semiconductor layer on the second semiconductor layer; and (g) forming the second conductor film over the substrate after the step (f) has been performed.
In this method, the semiconductor device can be formed easily. Particularly, in the step (e), the first insulator film to be a base undercoat insulating film is thinner than the center portion of the base layer, and the second semiconductor layer can be easily grown epitaxially to come into contact with the lower edge of a first conductor film.
The method may further include the step of patterning the first conductor film to form the base extended electrode of the bipolar transistor and a gate electrode for an MIS transistor at a time. Then, a BiCMOS device can be formed in a fewer number of process steps.
The method may further include the step of removing an oxide film from an exposed part of the first conductor film by performing an annealing process in an ultra high vacuum between the steps (d) and (e), thereby making a part of the first conductor film, hanging from the lower edge thereof around the periphery of the first opening, come into contact with the first semiconductor layer. In this manner, the stress, resulting from the difference in thermal expansion coefficient between the second semiconductor layer and first insulator film, can be further reduced.
The first semiconductor layer may be an Si layer. A single crystal SiGe layer may be formed as the second semiconductor layer in the step (e). And a single crystal Si layer may be formed as the third semiconductor layer in the step (f). As a result, an Si/SiGe hetero bipolar transistor can be formed.
The first semiconductor layer may be an Si layer. A single crystal SiGeC layer may be formed as the second semiconductor layer in the step (e). And a single crystal Si layer may be formed as the third semiconductor layer in the step (f). Then, by controlling the composition of SiGeC single crystals in the step (e), the stress applied to the second semiconductor layer and the strain of the bipolar transistor can be controlled appropriately and easily.